This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-069231, filed Mar. 13, 2000; and No. 2001-045331, filed Feb. 21, 2001, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a semiconductor device of a multi-layered wiring structure and a method of manufacturing the same.
In recent years, a Cu wiring has come to be used in the formation of a multi-layered wiring such as a logic article in accordance with miniaturization of the element.
A Cu wiring was formed in the past as follows. In the first step, a contact hole or a via hole is formed in an interlayer film, followed by filling the contact hole or the via hole with a metal film such as a W film. The metal film is planarized, followed by depositing again a metallic material for the wiring such as copper and subsequently patterning the deposited metal layer so as to form the wiring.
In recent years, however, a structure called a dual damascene structure has come to be employed in the Cu wiring. The dual damascene structure is a structure formed as follows. In the first step, a contact hole or a via hole and a groove corresponding to a wiring is formed in an interlayer film, followed by burying a metal film such as a copper film in the contact hole or in the via hole and the groove. The buried metal film is planarized by CMP (Chemical Mechanical Polish) so as to form a desired wiring.
The dual damascene structure described above includes a first method in which the contact hole is formed after formation of the groove and a second method in which the groove is formed after formation of the contact hole.
FIGS. 11 to 13 are cross sectional views collectively showing the method of manufacturing a semiconductor device by the first method noted above.
In the first step, a lower layer wiring 21 is selectively formed on an underlying substrate (not shown), followed by forming an interlayer film 22 on the entire surface and subsequently forming an organic antireflection film 23 on the interlayer film 22, as shown in FIG. 11. Further, the antireflection film 23 is coated with a resist film 24, followed by patterning the resist film 24. Still further, the antireflection film 23 and the interlayer film 22 are removed with the patterned resist film 24 used as a mask so as to form a groove 25. After formation of the groove 25, the resist film 24 is removed.
Then, an antireflection film 26 is formed again on the entire surface, followed by forming again a resist film 27 on the antireflection film 26, as shown in FIG. 12. As a result, the groove 25 is filled with the antireflection film 26 and the resist film 27. It should be noted that, since the groove 25 is formed in the interlayer film 22, the antireflection film 26 formed within the groove 25 fails to be made uniform in thickness. Further, the nonuniformity in the thickness of the antireflection film 26 causes the resist film 27 within the groove 25 to be nonuniform.
In the next step, the resist film 27 is patterned by lithography so as to form a contact hole 28 above the groove 25, as shown in FIG. 13.
In the first method of the conventional technology described above, it is necessary to pattern the resist film 27 to permit at least a part of the contact hole 28 to be positioned inside the groove 25. However, it is difficult to form a fine pattern of the contact hole 28 because that portion of the resist film 27 which is exposed to light is nonuniform in thickness.
FIGS. 14 to 17 are cross sectional views collectively showing a method of manufacturing a semiconductor device according to the second method of the conventional technology.
In the first step, a lower layer wiring 31 is selectively formed on an underlying substrate (not shown), followed by forming an interlayer film 32 on the entire surface and subsequently forming an organic antireflection film 33 on the interlayer film 32, as shown in FIG. 14. Then, the antireflection film 33 is coated with a resist film 34, followed by patterning the resist film 34. Further, the antireflection film 33 and the interlayer film 32 are removed with the patterned resist film 34 used as a mask so as to expose the surface of the lower layer wiring 31 to the outside. As a result, a contact hole 35 is formed in the interlayer film 32. Then, the resist film 34 and the antireflection film 33 are removed.
In the next step, an antireflection film 36 is formed again on the entire surface, as shown in FIG. 15. As a result, antireflection films 36a and 36b are formed on the interlayer film 32 and the lower layer wiring 31, respectively. Then, each of the antireflection films 36a and 36b is coated again with a resist film 37. It should be noted that, since the contact hole 35 has a high aspect ratio, the entire contact hole 35 is not filled completely with the antireflection film 36b. To be more specific, the bottom surface of the contact hole 35 is covered with the antireflection film 36b, and the resist film 37 is formed on the antireflection film 36b, thereby filling completely the contact hole 35.
Then, the resist film 37 is patterned by lithography, followed by removing the antireflection films 36a, 36b and an edge portion 32a of the interlayer film 32 with the patterned resist film 37 used as a mask, as shown in FIG. 16. In this case, the antireflection film 36b partly remains unremoved within the contact hole 35. The remaining antireflection film 36b serves to protect the bottom of the contact hole 35 in the subsequent step of forming a groove 38. Therefore, it is convenient for a part of the antireflection film 36 to remain unremoved within the contact hole 35.
In the next step, the interlayer film 32 and the antireflection film 36b are removed by an anisotropic etching such as RIE (Reactive Ion Etching) with the resist film 37 used as a mask so as to form the groove 38, as shown in FIG. 17. A side wall protective film 39 is formed on the side wall of each of the contact hole 35 and the groove 38 so as to maintain the anisotropy in performing the RIE treatment. As a result, after formation of the groove 38, a thin projecting portion, or fence, 40 of the interlayer film 32 extending along the side wall of the contact hole 35 is formed in the stepped portion between the contact hole 35 and the groove 38 under the influence of the side wall protective film 39.
As described above, in the second method of the conventional technology, the fence 40 is formed in forming the groove 38. What should be noted is that the fence 40 gives rise to the problem that the resistance between the contact hole 35 and a wiring (not shown) is increased or the region between the contact hole 35 and the wiring is rendered nonconductive. On the other hand, it is certainly possible to remove the fence 40 by the etching with, for example, a chemical solution. In this case, however, the groove 38 and the contact hole 35 are also etched, giving rise to the problem that the groove 38 and the contact hole 35 are enlarged.
As described above, in the first method of the conventional technology, it is difficult to pattern and process finely the resist film 27 in forming the contact hole 28 because the resist film 27 exposed to light in nonuniform in thickness. On the other hand, in the second method of the conventional technology, it is difficult to process finely the interlayer film 32 in forming the groove 38 because the surface to be etched (interlayer film 32) is not flat.
It follows that, in forming the wiring of a dual damascene structure by the conventional technology, it is difficult to process finely both the contact hole and the groove, though any of the contact hole and the groove may be processed finely.
An object of the present invention, which has been achieved for resolving the above-noted problems, is to provide a semiconductor device that permits a fine processing for forming a contact hole and a groove, and a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, which permits achieving the above-noted problems, there is provided a method of manufacturing a semiconductor device, comprising the steps of selectively forming a wiring on a semiconductor substrate; forming a first interlayer film on the entire surface; forming a first antireflection film on the first interlayer film; forming a first resist film on the first antireflection film; patterning the first resist film, followed by removing the first antireflection film and the first interlayer film with the patterned first resist film used as a mask so as to form a contact hole exposing the surface of the wiring to the outside; removing the first resist film; forming a second antireflection film on the entire surface so as to cover at least the bottom surface of the contact hole; forming a second resist film on the second antireflection film; patterning the second resist film to permit the second resist film to remain on the contact hole; removing the second antireflection film with the patterned second resist film used as a mask so as to expose the surface of the first interlayer film to the outside; forming a second interlayer film on the entire surface so as to cover the patterned second resist film and the second antireflection film; removing the second interlayer film so as to expose at least the entire surface of the patterned second resist film to the outside; and removing the patterned second resist film and the second antireflection film so as to form a groove in the second interlayer film.
In the manufacturing method of a semiconductor device according to the first aspect of the present invention, it is desirable for the second interlayer film to be formed of an SOG film of a coating type having a dielectric constant lower than that of the first interlayer film.
Also, in the manufacturing method of a semiconductor device according to the first aspect of the present invention, it is desirable for each of the first and second interlayer films to be formed of an organic film.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of selectively forming a wiring on a semiconductor substrate; forming a first interlayer film on the entire surface; forming a first antireflection film on the first interlayer film; forming a first resist film on the first antireflection film; patterning the first resist film, followed by removing the first antireflection film and the first interlayer film with the patterned first resist film used as a mask so as to form a contact hole exposing the surface of the wiring to the outside; removing the first resist film; forming a lower film of a second antireflection film on the entire surface so as to fill the contact hole; forming an upper film of the second antireflection film on the lower film of the second antireflection film; forming a second resist film on the upper film of the second antireflection film; patterning the second resist film to permit the second resist film to remain on the contact hole; patterning the upper film of the second antireflection film with the patterned second resist film used as a mask; patterning the lower film of the second antireflection film with the patterned upper film of the second antireflection film used as a mask so as to expose the surface of the first interlayer film to the outside; forming a second interlayer film on the entire surface so as to cover the upper film and the lower film of the second antireflection film; removing the second interlayer film and the upper film of the second antireflection film so as to expose at least the entire upper surface of the lower film of the second antireflection film; and removing the lower film of the second antireflection film so as to form a groove in the second interlayer film.
In the manufacturing method of a semiconductor device according to the second aspect of the present invention, it is desirable for each of the second interlayer film and the upper film of the second antireflection film to be formed of an SOG film.
Also, in the manufacturing method of a semiconductor device according to the second aspect of the present invention, it is desirable for the second interlayer film to be formed of a film having a dielectric constant lower than that of the first interlayer film and to consist of a film of a coating type.
Also, in the manufacturing method of a semiconductor device according to the second aspect of the present invention, it is desirable for the lower film of each of the first antireflection film and the second antireflection film to be formed of an organic film.
Also, in the manufacturing method of a semiconductor device according to the second aspect of the present invention, it is possible for the upper film and the lower film of the second antireflection film to be patterned collectively with the patterned second resist film used as a mask.
Further, in the manufacturing method of a semiconductor device according to the second aspect of the present invention, it is possible for the second interlayer film to be formed with the second resist film left unremoved and for the second resist film to be removed together with the second interlayer film and the upper film of the second antireflection film in the step of exposing at least the entire upper surface of the lower film of the second antireflection film to the outside.
According to a third aspect of the present invention, there is provided a semiconductor device, comprising a wiring formed selectively on a semiconductor substrate; a first interlayer film formed on the semiconductor substrate; a second interlayer film formed on the first interlayer film; a contact hole formed in the first interlayer film and exposing the surface of the wiring to the outside; and a groove formed in the second interlayer film positioned above the contact hole and having an opening larger than the opening of the contact hole.
In the semiconductor device according to the third aspect of the present invention, it is desirable for the second interlayer film to be formed of an SOG film of a coating type having a dielectric constant lower than that of the first interlayer film.
As described above, the present invention provides a semiconductor device that permits a fine processing in forming a contact hole and a groove and a method of manufacturing the particular semiconductor device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.